B. E.
Fifth Sefnester Examination, May-2007 MICROPROCESSeRAND INTERFACING
Note ~ Attempt any five questions. All questions qmy equal marks. All questions' <;:arry equal marks. All questions carry equal marks. Q. 1. (a) Give vector interrlJptsystem of8()86. '
\ , ,
Ans.lnterrupt Pointer (dr Ve,ctor): I K bytes of memory from 00000 to 003FF (hex) is set aside to store the starting addresses of inte'rrupt service subroutineS in an 8086 based system. To store the starting address of each ISS, four bytes of memory space is required: two bytes to store the values for CS and two bytes for IP .
values. Thus lK bytes of memory space can store the starting addresses of256 -lSS. The starting address of an ISS stored in the 1 KB memory space is called interrupt pointer or interrupt vector. The I KB memory space acts as a table to store the starting addresses ofISS. This table is called the interrupt pointer table.,
The 256 interrupt pointers have been numbered from 0 to 255. The number assigned to an interrupt pointer is called the type of the corresponding interrupt. For example, type 0 interrupt, type 1 interrupt, type 2 interrupt,...., and so on. Th~ starting address of the iss for type 0 interrupt is 00000 hex, for type 1 Interrupt is 00004 hex, for type 2 interrupt is 00008, and so on. Figure 2.7 shows the interrupt pointers forJa'ble for 8086. The first five pointers are dedicated interrupt pointers for specific interrupts. They are for divide-by-zero, single-step control, nonmaskable interrupt NMI, breakpoint, andpverflow intetrupt. The Intel has kept reserved the next 27 interrupts, trom type 5 to type 31, for other advanced microprocessors or they can be used for some spe\,:ial interrupts' in an 8086 based system. The system designer can used these interrupt pointers. The in,icroproces- .
, SOl' will respond accordingly. The upper 224 interrupts, from type 32 to type 255, are available to users for hardware and software interrupts. '1C
", ..
When an interrupt occurs, the 8086 pushes the flag register on the stack, TF and IF are cleared which , disable the single-step and INTR interrupt, and the contents ofCS and IP are pushed on the stack. Thereafter, the program jumps automatically to the starting address of the ISS: In .case of a hardware interrupt, the interrupting device or interrupt controlIe~ gives the type of the interrupt· in response to the
. INT A Signals sentto the I/O device or interrupt controller. In case of so~are interrupt, the type depends onthe instruction usedfor the purpose. At the end of an ISS, IRET instruc,tion is used. When IRET is ~xecuted, i,t pops the contents of IP and then CS, Finally it pops flags into flag register from the stack. When flags are , restored, IF and TF are restored to the previous values (i.e. before the interrupt occurred). Suppose IF and TF \ ,were enabled before interrupt occurred, they-will be enabled again after return to the main program from ISS. . During the execution of the main progra~ from ISS. Duringthe execution ofISS, IF and TF are cleated resulting in disl,ibling ofINTR and single step interrupt. ' ' ,
Q. 1. (b) Write an assembly language program (8085) to stimulate a flashing yellow light with 750,ms
on time. Use D7 to controHhe light.
2. (Ii) Which flags will be affected, after the execution offollowing instructions. '
(i) MOVA,B
(fi)ORA B
~,-
104
B. E. Fifth Semester Solyed' Papers, Dec~-2006
bus:
DO - D7 -Bidirectional data bus. Control, status and interrupt vector informatio~ .is transferred via this
CASo - CAS7 -slave program/enable buffer~
INT -Interrupt. It is used to interrupt CPU.
INT k-Interrupt acknowledge. 0
IRo - IR7 ~Address line. I! acts in conjunction with RD, WR and CS. The intel 8259 uses iHo
interpret command words the CPU writes and status the.CPU w~nis to read.
(b) DMA Process: It is a process of comrimnication or data transfer controlled by an external peripheral.
In situations in which the rriicroprocessor controlled data transfer is too slow, the D!V1A is generally used, e.g.
dat<1 style="FONT-WEIGHT: bold">B. E. Fifth Semester Solved Paper:;, May-2007
(Hi) CMP R (iv)XRAA (v)HLT (vi)DCXD Ans. (i) Mov A,B : No flags are affected , (ii) ORAB : Z,S, P are modified to reflect the results Of the operation.-AC & CY are reset.
(iii) CMPR : S, P, Ac are also modified in addition to Z & tY to reflect the results of the operation" (iv) XRAA : Z, S, P are altered to reflectthe results of operation, CY & AC are reset.
(v) HLT : No flags are affected, (vi) DCXO : No flags are affected, ' Q. 2.(b) Explain block diagram of 8086. Also explain how demultiplexing of address & data bus is carried out. ,
~ ~:-: - -.~ .,.. - -: - - -: ,- -: '- -:- - -. -----: .:-,... -: -: - - - - - - - :... - - - - - -I
G- BUS ' 'J .', I .
, ,
I I I I"STRUCTIONI ±-l ST.RE/\.M :
L. RYrE 1 ~QVl::V£ I
1--, ,
_..:_____'-_J
I r I 1 ,I
,
I 1 1 ' I I I I I r I 'I I I
I ' ' :; " , '-I -,' v
t., ,SI '.. , ; . ','
I' DI; . ' I
: . , ' U ,:
1_ _ _..J _ __.~:''"''!'!.~'''''''!'''~~.~:- ~_~ _'~ _ _ -::_ ~._ "'!'" _;-_ __ ...~.__::" ~ ,_'" ~ '.,; _ _ _ _ ___ __'.
8086' internal block di'agnim
, .
Ans. 8086 Internal Architecture:
Es . Cs 55 Ds' r
,---------------.,..
I i I I I
- _''':'__._'..,,_-,_ - - __I
A-BUS
lEU I
AH
~
en DH,
'AI. Bl, abL,
'~ ."--,--,:"
Microprocessor and Interfacing
107
8086 CPU is decided into two il)dependent'functional parts, (i) The Bus interface unit'(BIU) (2) Execution unit. (EU)
Dividing. the word between t~ese two units speds of processing.
81U: Sends out fetches instructions;from memory reads data from pat1S and memo!)', and writer qata to parts and memory. . '
The BIU handles all transfers of data' and address~s on the buses for the execution unit.
The DIU contains:
(i) Queue: BIU fetches up to si~ instruction bytes for the instructions, which are not executed by the execution unit.
The B[U stores these perfected bytes in a first in first out register set called a queue.
The lJ1akes the processing faster than any other processor.
(2) ~egment Registers': The four ~eparate register in the BIU are. used to hold the upper] 6 bits of the starting addresses of four memory segments that the 8086 is working with at the particular time. The four.
segment register are the code segment (CS) register, stack segment register (SS), the extra. segment register (ES), data segment register (OS).
.
The four segments can be operlapped also.
The 8086 eccesses memory; the BIU produ{;es the required 20-bit physical addr~ss by adderingan offset to a segment base value· represnted by the content of of1$: of the segment register. .
(3). Instruction Pointer: (IP) register: [t holds the 16-bit addresses, or offset of the next instruction byte is to be fetche.d from.
The Execution (EU): Tells the BIU where to fetch instructions or data from, address instructions, and . excludes instructions.
T!1e E.U contains circuity which directs ~nternal operations.
. " ,". -'.
A decoder translates instructions (etched from memory into a 'seves of actions which the EV carries out.
EU has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement, complement as shift binary nos.
. FL~G Regi~ter : A flag is a flip flop which indicates some condition produced by the execution of an instruction or controls certain operation of the EU. .
..A l6-bit flag register in EU contail)s nine active flags; the are six conditional flag ~nd three control flags,
Fifth Sefnester Examination, May-2007 MICROPROCESSeRAND INTERFACING
Note ~ Attempt any five questions. All questions qmy equal marks. All questions' <;:arry equal marks. All questions carry equal marks. Q. 1. (a) Give vector interrlJptsystem of8()86. '
\ , ,
Ans.lnterrupt Pointer (dr Ve,ctor): I K bytes of memory from 00000 to 003FF (hex) is set aside to store the starting addresses of inte'rrupt service subroutineS in an 8086 based system. To store the starting address of each ISS, four bytes of memory space is required: two bytes to store the values for CS and two bytes for IP .
values. Thus lK bytes of memory space can store the starting addresses of256 -lSS. The starting address of an ISS stored in the 1 KB memory space is called interrupt pointer or interrupt vector. The I KB memory space acts as a table to store the starting addresses ofISS. This table is called the interrupt pointer table.,
The 256 interrupt pointers have been numbered from 0 to 255. The number assigned to an interrupt pointer is called the type of the corresponding interrupt. For example, type 0 interrupt, type 1 interrupt, type 2 interrupt,...., and so on. Th~ starting address of the iss for type 0 interrupt is 00000 hex, for type 1 Interrupt is 00004 hex, for type 2 interrupt is 00008, and so on. Figure 2.7 shows the interrupt pointers forJa'ble for 8086. The first five pointers are dedicated interrupt pointers for specific interrupts. They are for divide-by-zero, single-step control, nonmaskable interrupt NMI, breakpoint, andpverflow intetrupt. The Intel has kept reserved the next 27 interrupts, trom type 5 to type 31, for other advanced microprocessors or they can be used for some spe\,:ial interrupts' in an 8086 based system. The system designer can used these interrupt pointers. The in,icroproces- .
, SOl' will respond accordingly. The upper 224 interrupts, from type 32 to type 255, are available to users for hardware and software interrupts. '1C
", ..
When an interrupt occurs, the 8086 pushes the flag register on the stack, TF and IF are cleared which , disable the single-step and INTR interrupt, and the contents ofCS and IP are pushed on the stack. Thereafter, the program jumps automatically to the starting address of the ISS: In .case of a hardware interrupt, the interrupting device or interrupt controlIe~ gives the type of the interrupt· in response to the
. INT A Signals sentto the I/O device or interrupt controller. In case of so~are interrupt, the type depends onthe instruction usedfor the purpose. At the end of an ISS, IRET instruc,tion is used. When IRET is ~xecuted, i,t pops the contents of IP and then CS, Finally it pops flags into flag register from the stack. When flags are , restored, IF and TF are restored to the previous values (i.e. before the interrupt occurred). Suppose IF and TF \ ,were enabled before interrupt occurred, they-will be enabled again after return to the main program from ISS. . During the execution of the main progra~ from ISS. Duringthe execution ofISS, IF and TF are cleated resulting in disl,ibling ofINTR and single step interrupt. ' ' ,
Q. 1. (b) Write an assembly language program (8085) to stimulate a flashing yellow light with 750,ms
on time. Use D7 to controHhe light.
2. (Ii) Which flags will be affected, after the execution offollowing instructions. '
(i) MOVA,B
(fi)ORA B
~,-
104
B. E. Fifth Semester Solyed' Papers, Dec~-2006
bus:
DO - D7 -Bidirectional data bus. Control, status and interrupt vector informatio~ .is transferred via this
CASo - CAS7 -slave program/enable buffer~
INT -Interrupt. It is used to interrupt CPU.
INT k-Interrupt acknowledge. 0
IRo - IR7 ~Address line. I! acts in conjunction with RD, WR and CS. The intel 8259 uses iHo
interpret command words the CPU writes and status the.CPU w~nis to read.
(b) DMA Process: It is a process of comrimnication or data transfer controlled by an external peripheral.
In situations in which the rriicroprocessor controlled data transfer is too slow, the D!V1A is generally used, e.g.
dat<1 style="FONT-WEIGHT: bold">B. E. Fifth Semester Solved Paper:;, May-2007
(Hi) CMP R (iv)XRAA (v)HLT (vi)DCXD Ans. (i) Mov A,B : No flags are affected , (ii) ORAB : Z,S, P are modified to reflect the results Of the operation.-AC & CY are reset.
(iii) CMPR : S, P, Ac are also modified in addition to Z & tY to reflect the results of the operation" (iv) XRAA : Z, S, P are altered to reflectthe results of operation, CY & AC are reset.
(v) HLT : No flags are affected, (vi) DCXO : No flags are affected, ' Q. 2.(b) Explain block diagram of 8086. Also explain how demultiplexing of address & data bus is carried out. ,
~ ~:-: - -.~ .,.. - -: - - -: ,- -: '- -:- - -. -----: .:-,... -: -: - - - - - - - :... - - - - - -I
G- BUS ' 'J .', I .
, ,
I I I I"STRUCTIONI ±-l ST.RE/\.M :
L. RYrE 1 ~QVl::V£ I
1--, ,
_..:_____'-_J
I r I 1 ,I
,
I 1 1 ' I I I I I r I 'I I I
I ' ' :; " , '-I -,' v
t., ,SI '.. , ; . ','
I' DI; . ' I
: . , ' U ,:
1_ _ _..J _ __.~:''"''!'!.~'''''''!'''~~.~:- ~_~ _'~ _ _ -::_ ~._ "'!'" _;-_ __ ...~.__::" ~ ,_'" ~ '.,; _ _ _ _ ___ __'.
8086' internal block di'agnim
, .
Ans. 8086 Internal Architecture:
Es . Cs 55 Ds' r
,---------------.,..
I i I I I
- _''':'__._'..,,_-,_ - - __I
A-BUS
lEU I
AH
~
en DH,
'AI. Bl, abL,
'~ ."--,--,:"
Microprocessor and Interfacing
107
8086 CPU is decided into two il)dependent'functional parts, (i) The Bus interface unit'(BIU) (2) Execution unit. (EU)
Dividing. the word between t~ese two units speds of processing.
81U: Sends out fetches instructions;from memory reads data from pat1S and memo!)', and writer qata to parts and memory. . '
The BIU handles all transfers of data' and address~s on the buses for the execution unit.
The DIU contains:
(i) Queue: BIU fetches up to si~ instruction bytes for the instructions, which are not executed by the execution unit.
The B[U stores these perfected bytes in a first in first out register set called a queue.
The lJ1akes the processing faster than any other processor.
(2) ~egment Registers': The four ~eparate register in the BIU are. used to hold the upper] 6 bits of the starting addresses of four memory segments that the 8086 is working with at the particular time. The four.
segment register are the code segment (CS) register, stack segment register (SS), the extra. segment register (ES), data segment register (OS).
.
The four segments can be operlapped also.
The 8086 eccesses memory; the BIU produ{;es the required 20-bit physical addr~ss by adderingan offset to a segment base value· represnted by the content of of1$: of the segment register. .
(3). Instruction Pointer: (IP) register: [t holds the 16-bit addresses, or offset of the next instruction byte is to be fetche.d from.
The Execution (EU): Tells the BIU where to fetch instructions or data from, address instructions, and . excludes instructions.
T!1e E.U contains circuity which directs ~nternal operations.
. " ,". -'.
A decoder translates instructions (etched from memory into a 'seves of actions which the EV carries out.
EU has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement, complement as shift binary nos.
. FL~G Regi~ter : A flag is a flip flop which indicates some condition produced by the execution of an instruction or controls certain operation of the EU. .
..A l6-bit flag register in EU contail)s nine active flags; the are six conditional flag ~nd three control flags,
